This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device with MIS (Metal-Insulator-Semiconductor) field effect transistors and process for fabricating the semiconductor integrated circuit device.
Plural circuit elements are integrated on a semiconductor substrate, and are selectively connected for forming an integrated circuit. The integrated circuit is broken down into a signal interface and a functional circuit. Signals are transferred between the functional circuit and the outside thereof through the signal interface. The functional circuit processes signals carried with pieces of data information, and temporarily stores the result of the data processing.
The data processing is assigned to an arithmetic and logic circuit, and a memory circuit stores the results. Typical examples of the memory circuit are a dynamic random access memory and a static random access memory, and the arithmetic and logic circuit is, by way of example, implemented by CMOS (Complementary Metal Oxide Semiconductor) logic gates. MOS (Metal Oxide Semiconductor) field effect transistors are, by way of example, used for the signal interface. Thus, field effect transistors are major circuit components of the integrated circuit.
One of the goals in the technical field is to operate the field effect transistors at high speed under low power voltage. A field effect transistor with a thin gate insulating layer is suitable for the technical goal. The miniaturization, high-speed and low power consumption are still required for the semiconductor integrated circuit device. The functional circuit are formed by using the component field effect transistors, the gate insulating layers of which get thinner and thinner for operating under the low power voltage. However, the solution is less employable in the signal interface. The external signals are applied to the signal interface, and the voltage range of the external signals is independent of the internal power supply system in the integrated circuit. Thus, the external signal is a dominating factor in the signal interface. In this situation, the component field effect transistors of the signal interface are designed separately from those of the functional circuit, and the gate insulating layers thereof are usually thicker than those of the component field effect transistors of the functional circuit. In a semiconductor integrated circuit device commercially obtainable, the component field effect transistors of the signal interface are designed to have the gate insulating layers of 7 nanometers thick, and the component field effect transistors of the functional circuit are designed to have the gate insulating layers of 4 nanometers thick.
The design and research efforts are been made for the field effect transistors with the emphasis put on faster transistors. The speed-up is not constantly required over the integrated circuit. The speed-up is more important to the arithmetic and logic circuit than another part of the integrated circuit. The gate insulating layer is going to reduce from 7 nanometers thick to 5 nanometers thick for the circuit components of the signal interface and from 4 nanometers thick to 2 nanometers thick for the functional circuit.
The thin gate insulating layers surely accelerate the switching actions of the component field effect transistors. However, a problem is encountered in the component field effect transistors in the leakage current flowing through the thin gate insulating layers. FIG. 1 illustrates the leakage current density in terms of the thickness Tox of the gate insulating layer formed of silicon oxide. The axis of abscissas is indicative of the thickness of the gate insulating layer formed of silicon oxide. On the other hand, the axis of coordinates is indicative of the leakage current density. When the gate insulating layer is biased with 1.5 volts, the leakage current density is varied in inversely exponentially proportional to the thickness of the gate insulating layer. Thus, the thin gate insulating layers give rise to increase of the leakage current flowing therethrough.
The leakage current is undesirable for the integrated circuit. First, the power consumption is increased in the idling state. Second, the thin gate insulating layers are damaged or deteriorated due to the leakage current. Third, a piece of data information is destroyed when the field effect transistors form a memory cell. This means that the leakage current sets a limit to the thickness of the gate insulating layer. The limit is varied depending upon the operating environment of the field effect transistor such as, for example, the bias voltage and function of the associated circuitry.
As will be understood, an integrated circuit includes field effect transistors different in thickness, and the difference in thickness is dependent on the requirements for a circuitry. Although the manufacturer makes the gate insulating layers different in thickness between the component field effect transistors of the signal interface and the field effect transistors of the functional circuit both integrated on a semiconductor substrate, the difference in thickness is of the order of 3 nanometers thick. It is said that the limit to the gate insulating layers is 3 nanometers to 1 nanometer. Even if the manufacturer designs field effect transistors of an integrated circuit to have the gate insulating layers different in thickness of the order of 0.5 nanometer, the integrated circuit is not feasible. For example, a manufacturer is assumed to design field effect transistors with the gate insulating layers of 2.0 nanometers thick for the arithmetic and logic circuit and field effect transistors with the gate insulating layers of 2.5 nanometers thick for the memory circuit. The manufacturer fabricates the two kinds of field effect transistors different in thickness on a semiconductor substrate through the prior art process. However, the gate insulating layers are not properly fallen within the range around 2.0 nanometers thick and the range around 2.5 nanometers thick upon completion of the fabrication process. The gate insulating layers are randomly fallen within the range around 2.0 nanometers thick and the range around 2.5 nanometers thick, and it is impossible to discriminate the design intention from the field effect transistors fabricated on the semiconductor substrate. Thus, the difference of 1 nanometer thick is the limit to the gate insulating layers of the order of 4 nanometers thick or less in so far as the field effect transistors are fabricated through known process sequences.
Description is hereinbelow made on the prior art process sequences. The first prior art process is used for a semiconductor integrated circuit device having three regions assigned to different circuits. The first region is referred to as a core region, and a CMOS logic circuit is assigned to the core region. The second region is referred to as an SRAM (Static Random Access Memory) region, and the SRAM region is assigned to a static random access memory. The component field effect transistors of the CMOS logic circuit are different in thickness of the gate insulating layers from the component field effect transistors of the static random access memory. The third region is referred to as a peripheral region, and an input-and- output circuit is assigned to the peripheral region. The component field effect transistors of the input-and-output circuit are different in thickness of the gate insulating layers from those of the CMOS logic circuit and those of the static random access memory.
FIGS. 2A to 2J, 3A to 3J and 4A to 4J illustrate the first prior art process for fabricating the semiconductor integrated circuit device. FIGS. 2A to 2J show a cross section of the core region, and a gate insulating layer is adapted to 1.8 nanometers thick. FIGS. 3A to 3J show a cross section of the SRAM region, and a gate insulating layer is adapted to 4.0 nanometers thick. FIGS. 4A to 4J show a cross section of the peripheral region, and a gate insulating layer is adapted to 6.0 nanometers thick. The cross sections in FIGS. 2A, 3A and 4A are achieved at the end of the first step of the first prior art process, and FIGS. 2B, 3B and 4B show the cross sections at the end of the second step. Similarly, FIGS. 2C/3C/4C, 2D/3D/4D, 2E/3E/4E, . . . 2J/3J/4J shows the cross sections at the end of the third step, the end of the fourth step, the end of the fifth step, . . . and the end of the tenth step, respectively.
The first prior art process starts with preparation of a silicon substrate 1. A trench isolating region 2 are formed in a surface portion of the silicon substrate 1, and defines active areas in the three regions. There is not any difference between the cross sections. The resultant structure is shown in FIGS. 2A, 3A and 4A.
Subsequently, the semiconductor substrate 1 is placed in a furnace chamber (not shown), and oxidation atmosphere is created in the furnace chamber. Oxygen is 100 percent in the oxidation atmosphere. The silicon substrate 1 is exposed to the oxidation atmosphere for 30 minutes. Then, silicon oxide layers 63 are thermally grown to 4.5 nanometers thick in the active areas as shown in FIGS. 2B, 3B and 4B.
Subsequently, photo-resist solution is spread over the entire surface of the resultant structure, and is baked so as to form a photo-resist layer. A pattern image is transferred to the photo-resist layer, and forms a latent image in the photo-resist layer. The latent image is developed, and a photo-resist mask 35 is formed from the photo-resist layer. Thus, the photo-resist mask 35 is patterned through the photo-lithography, and only the active area in the peripheral region is covered with the photo-resist mask as shown in FIGS. 2C, 3C and 4C.
The resultant structure is subjected to an etching. The photo-resist mask 35 prevents the silicon oxide layer 63 in the peripheral region from the etchant. However, the silicon oxide layers 63 in the core region and the SRAM region are etched away. The silicon is exposed to the active area in the core region and the active area in the SRAM region, again. The resultant structure is shown in FIGS. 2D, 3D and 4D.
Subsequently, the photo-resist mask 35 is stripped off, and the silicon oxide layer 63 is exposed to the active area in the peripheral region (see FIGS. 2E, 3E and 4E). The resultant structure is oxidized, again. The oxidizing atmosphere is created by using the oxygen at 100 percent, and the silicon substrate 1 is thermally oxidized at 800 degrees in centigrade for 15 minutes. Then, silicon oxide layers 64 are grown to 3.0 nanometers thick on the active area in the core region and on the active area in the SRAM region (see FIGS. 2F and 3F), and the silicon oxide layer 63 in the peripheral region is increased in thickness to 5.5 nanometers thick. The active area in the peripheral region has been already covered with the silicon oxide layer 63, and the oxygen is diffused through the silicon oxide layer 63 until the boundary between the silicon and the silicon oxide. This means that the silicon substrate is less oxidized in the peripheral region rather than the core/SRAM regions. Thus, the growth rate of silicon oxide is lowered when the silicon oxide is increased in thickness. This is the reason why the increment of the silicon oxide layer 63 is less than the thickness of the silicon oxide layers 64. The silicon oxide layer in the peripheral region is labeled with reference numeral 65 as shown in FIG. 4F.
Subsequently, a photo-resist mask 36 is patterned on the resultant structure by using the photo-lithography, and the active area in the SRAM region and the active area in the peripheral region are covered with the photo-resist mask 36 as shown in FIGS. 2G, 3G and 4G.
The resultant structure is subjected to the etching. Although the photo-resist mask 36 prevents the silicon oxide layers 64/65 in the SRAM/peripheral regions from the etchant, the silicon oxide layer 64 is etched away from the core region, and the silicon is exposed to the active area in the core region, again. The resultant structure is shown in FIGS. 2H, 3H and 4H.
The photo-resist mask 36 is stripped off. The silicon oxide layers 64 and 65 are exposed to the active areas in the SRAM/peripheral regions, and the silicon is exposed to the active area in the core region (see FIGS. 2I, 3I and 4I).
The resultant structure is placed in the furnace chamber, again. Oxi-nitriding atmosphere is created by using oxygen at 50 percent and nitrogen monoxide (NO) at 50 percent, and the thermal oxi-nitrization is carried out in the oxi-nitrizing atmosphere at 1000 degrees in centigrade for 30 to 60 seconds. Then, nitrogen-containing silicon oxide or silicon oxynitride is thermally grown on the active areas in the three regions. The silicon oxynitride is different from a silicon oxide layer and a silicon nitride layer laminated on each other. A gate insulating layer 47 of silicon oxynitride is grown to 1.8 nanometers thick on the active area in the core region (see FIG. 2J). Further, the silicon oxynitride is grown to 1 nanometer thick and 0.5 nanometer thick in the boundary between the silicon and the silicon oxide in the SRAM/peripheral regions, respectively, and the active areas in the SRAM/peripheral regions are respectively covered with gate insulating layers 55 and 56. The gate insulating layer 55 is 4.0 nanometers thick, and the gate insulating layer 56 is 6.0 nanometers thick (see FIGS. 3J and 4J).
Thus, the gate insulating layer 55 is thicker than the gate insulating layer 47 by 2.2 nanometers. Thus, the gate insulating layers 47/55/56 are different in thickness through the first prior art process, and the difference is 2.0 to 2.2 nanometers. Thus, the manufacturer merely achieves the difference ranging from 1 nanometer thick to 2 nanometers thick through the first prior art process. In other words, it is impossible to make a gate insulating layer in the SRAM region differ from a gate insulating layer in the core region by 0.5 nanometer thick.
It is said that manufacturers grow thin films different in thickness by 1-2 nanometers thick by using the current thin film growing technologies such as the thermal oxidation. Assuming now that silicon oxide layers are grown through the thermal oxidation, the manufacturer expects the thermal oxidation process to achieve the thickness 1-2 nanometers different from each other by controlling the conditions of the thermal oxidation. When silicon oxide is grown at the boundary between silicon and silicon oxide, the silicon layer decelerated the growth rate. If the silicon oxide layer to be grown on the silicon layer is relatively thick, the oxidation is continued for a relatively long time, and the difference between the silicon oxide layers is decreased from the initial value. However, the silicon oxide layer to be grown on the silicon layer is relatively thin, the oxidation is completed within a short time, and the decrement from the initial difference is negligible. In other words, the manufacturer can not rely on the deceleration of the growth as long as the silicon oxide layers are thin. Thus, the thin film growth technologies still sets the limit to the difference in thickness between the gate insulating layers formed through the first prior art process.
The second prior art process is disclosed in Japanese Patent Publication of Unexamined Application No. 10-335656. The second prior art process is featured by the step of introducing impurity into a semiconductor substrate. The growth rate of silicon oxide is varied by the impurity introduced into the silicon substrate. The second prior art process aims at reducing the photo-lithographic steps and decreasing the stress due to the heat treatment for the gate insulating layers. This means that the second prior art process did not aim at the difference less than 1 nanometer thick between ultra thin gate insulating layers of the order of 4.0 nanometers. Nevertheless, if gate insulating layers are differently grown on a semiconductor substrate through the second prior art process, the difference between the gate insulating layers would be less than that between the gate insulating layers grown through the first prior art process, because the relatively thin gate insulating layer and the relatively thick gate insulating layer are concurrently grown after the selective ion-implantation. However, a problem is encountered in the second prior art process in that the crystal structure of the semiconductor substrate is liable to be damaged due to the ion-implanted impurity such as argon, xenon, oxygen or nitrogen.
It is therefore an important object of the present invention to provide a semiconductor device, which includes gate insulating layers of field effect transistors of the order of 4 nanometers thick or less and different from one another by 1 nanometer thick or less.
It is also an important object of the present invention to provide a process for fabricating the field effect transistors on a semiconductor substrate.
To accomplish the object, the present invention proposes to use insulating material containing an oxidizing agent and a diffusion inhibitor.
In accordance with one aspect of the present invention, there is provided a semiconductor device fabricated on a semiconductor substrate comprising an integrated circuit including plural circuit components respectively having insulating layers formed of different kinds of dielectric material and different in thickness, the insulating layers of two of the plural circuit components are less than 4 nanometers thick, and the difference in thickness between the insulating layers of the two of the plural circuit components is less than 1 nanometer.
In accordance with another aspect of the present invention, there is provided a process for fabricating a semiconductor device, comprising the steps of a) preparing a substrate formed of semiconductor material and having plural portions selectively assigned to plural circuit components of an integrated circuit, b) growing a first insulating layer formed of a first kind of insulating material containing an oxidizing agent diffused therethrough and reactive with the semiconductor material and a diffusion inhibitor against the diffusion of the oxidizing agent on one of the plural portions of the substrate, c) growing a second insulating layer formed of a second kind of insulating material containing the oxidizing agent on the one of the plural portions and another portion of the substrate so as to form a first dielectric layer having at least the first and second insulating layers and a second dielectric layer different in thickness from the second insulating layer and having the second insulating layer for one of the plural circuit components and another of the plural circuit components, respectively, and d) completing the plural circuit components.